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1. general description the 74ALVT16601 is a high-performance bipolar complementary metal oxide semiconductor (bicmos) product designed for v cc operation at 2.5 v and 3.3 v with i/o compatibility up to 5 v. this device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. data ?ow in each direction is controlled by output enable ( oeab and oeba), latch enable (leab and leba), and clock (cpab and cpba) inputs. for a-to-b data ?ow, the device operates in the transparent mode when leab is high. when leab is low, the a-bus data is latched if cpab is held at a high or low level. if leab is low, the a-bus data is stored in the latch/?ip-?op on the low-to-high transition of cpab. when oeab is low, the outputs are active. when oeab is high, the outputs are in the high-impedance state. the clocks can be controlled with the clock enable inputs ( ceab and ceba). data ?ow for b-to-a is similar to that of a-to-b but uses oeba, leba and cpba. active bus hold circuitry is provided to hold unused or ?oating data inputs at a valid logic level. 2. features n 18-bit bidirectional bus interface n 5 v i/o compatible n 3-state buffers n output capability: +64 ma and - 32 ma n ttl input and output switching levels n input and output interface capability to systems at 5 v supply n bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs n live insertion and extraction permitted n power-up reset n power-up 3-state n no bus current loading when output is tied to 5 v bus n positive-edge triggered clock inputs n latch-up protection: u jesd78: exceeds 500 ma n esd protection: u mil std 883, method 3015: exceeds 2000 v u machine model: exceeds 200 v 74ALVT16601 18-bit universal bus transceiver; 3-state rev. 03 5 july 2005 product data sheet
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 2 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 3. quick reference data 4. ordering information table 1: quick reference data gnd = 0 v; t amb = 25 c. symbol parameter conditions min typ max unit v cc = 2.5 v t plh propagation delay an to bn or bn to an c l = 30 pf - 1.8 - ns t phl propagation delay an to bn or bn to an c l = 30 pf - 2.2 - ns c i input capacitance of control pins v i = 0 v or v cc 4- pf c io input/output capacitance of i/o pins v i/o = 0 v or v cc ; outputs disabled 8- pf i cc supply current outputs disabled - 40 - m a v cc = 3.3 v t plh propagation delay an to bn or bn to an c l = 50 pf - 1.9 - ns t phl propagation delay an to bn or bn to an c l = 50 pf - 2 - ns c i input capacitance of control pins v i = 0 v or v cc 4- pf c io input/output capacitance of i/o pins v i/o = 0 v or v cc ; outputs disabled 8- pf i cc supply current outputs disabled - 60 - m a table 2: ordering information type number package temperature range name description version 74ALVT16601dl - 40 c to +85 c ssop56 plastic shrink small outline package; 56 leads; body width 7.5 mm sot371-1 74ALVT16601dgg - 40 c to +85 c tssop56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364-1
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 3 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 5. functional diagram fig 1. logic symbol fig 2. iec logic symbol 001aad316 a7 a8 a9 a10 a11 a12 a13 a14 oeab oeba leab leba cpab cpba ceab ceba 1 2 55 56 29 30 28 21 20 19 a15 a16 a17 26 24 23 17 16 15 14 13 a0 a1 a2 a3 a4 a5 a6 12 10 9 8 6 5 3 b7 b8 b9 b10 b11 b12 b13 b14 36 37 38 b15 b16 b17 31 33 34 40 41 42 43 44 b0 b1 b2 b3 b4 b5 b6 45 47 48 49 51 52 54 27 3d 6d 4 g5 3 54 28 c6 30 5c6 29 g5 27 en4 en1 oeab ceab cpab leab g2 c3 2c3 g2 2 55 56 1 1 552 651 849 948 10 47 12 45 13 14 44 43 42 41 40 38 37 36 34 33 31 15 16 17 19 20 21 23 24 26 b1 b0 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 a1 a0 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 001aad317 oeba ceba cpba leba
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 4 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state fig 3. logic diagram 001aad249 ce 54 a0 id c1 to 17 other channels clk ce id b0 3 oeba 27 ceba 29 cpba 30 leba 28 leab 2 cpab 55 ceab 56 oeab 1 c1 clk
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 5 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 6. pinning information 6.1 pinning 6.2 pin description fig 4. pin con?guration 16601 oeab ceab leab cpab a0 b0 gnd gnd a1 b1 a2 b2 v cc v cc a3 b3 a4 b4 a5 b5 gnd gnd a6 b6 a7 b7 a8 b8 a9 b9 a10 b10 a11 b11 gnd gnd a12 b12 a13 b13 a14 b14 v cc v cc a15 b15 a16 b16 gnd gnd a17 b17 oeba cpba leba ceba 001aad247 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 table 3: pin description symbol pin description oeab 1 a-to-b output enable input (active low) leab 2 a-to-b latch enable input a0 3 data input or output (a side) gnd 4 ground (0 v) a1 5 data input or output (a side) a2 6 data input or output (a side) v cc 7 voltage supply a3 8 data input or output (a side)
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 6 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state a4 9 data input or output (a side) a5 10 data input or output (a side) gnd 11 ground (0 v) a6 12 data input or output (a side) a7 13 data input or output (a side) a8 14 data input or output (a side) a9 15 data input or output (a side) a10 16 data input or output (a side) a11 17 data input or output (a side) gnd 18 ground (0 v) a12 19 data input or output (a side) a13 20 data input or output (a side) a14 21 data input or output (a side) v cc 22 voltage supply a15 23 data input or output (a side) a16 24 data input or output (a side) gnd 25 ground (0 v) a17 26 data input or output (a side) oeba 27 b-to-a output enable input (active low) leba 28 b-to-a latch enable input ceba 29 b-to-a clock enable (active low) cpba 30 b-to-a clock input (active rising edge) b17 31 data input or output (b side) gnd 32 ground (0 v) b16 33 data input or output (b side) b15 34 data input or output (b side) v cc 35 voltage supply b14 36 data input or output (b side) b13 37 data input or output (b side) b12 38 data input or output (b side) gnd 39 ground (0 v) b11 40 data input or output (b side) b10 41 data input or output (b side) b9 42 data input or output (b side) b8 43 data input or output (b side) b7 44 data input or output (b side) b6 45 data input or output (b side) gnd 46 ground (0 v) b5 47 data input or output (b side) b4 48 data input or output (b side) b3 49 data input or output (b side) table 3: pin description continued symbol pin description
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 7 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 7. functional description 7.1 function table [1] h = high voltage level; l = low voltage level; x = dont care; z = high-impedance off-state; - = low-to-high clock transition [2] output level before the indicated steady-state input conditions were established. [3] output level before the indicated steady-state input conditions were established, provided that cpab or cpba was low before leab or leba went low. 8. limiting values v cc 50 voltage supply b2 51 data input or output (b side) b1 52 data input or output (b side) gnd 53 ground (0 v) b0 54 data input or output (b side) cpab 55 a-to-b clock input (active rising edge) ceab 56 a-to-b clock enable (active low) table 3: pin description continued symbol pin description table 4: function table [1] control input output ceab oeab leab cpab an bn ceb a oeb a leba cpba bn an xhxxx z xl hxl l hh lll - ll hh lllhx y [2] lx y [3] hllxx y [2] table 5: limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v v i input voltage [1] - 0.5 +7.0 v v o output voltage output in off-state or high-state [1] - 0.5 +7.0 v
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 8 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state [1] the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. recommended operating conditions i ik input diode current v i <0v - - 50 ma i ok output diode current v o <0v - - 50 ma i o output current output in low-state - 128 ma output in high-state - - 64 ma t stg storage temperature - 65 +150 c t j junction temperature [2] - 150 c table 5: limiting values continued in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit table 6: recommended operating conditions symbol parameter conditions min typ max unit v cc = 2.5 v 0.2 v v cc supply voltage 2.3 - 2.7 v v i input voltage 0 - 5.5 v v ih high-level input voltage 1.7 - - v v il low-level input voltage - - 0.7 v i oh high-level output current - - - 8ma i ol low-level output current none - - 8 ma current duty cycle 50 %; f 3 1 khz --24ma d t/ d v input transition rise or fall rate outputs enabled - - 10 ns/v t amb ambient temperature - 40 - +85 c v cc = 3.3 v 0.3 v v cc supply voltage 3.0 - 3.6 v v i input voltage 0 - 5.5 v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i oh high-level output current - - - 32 ma i ol low-level output current none - - 32 ma current duty cycle 50 %; f 3 1 khz --64ma d t/ d v input transition rise or fall rate outputs enabled - - 10 ns/v t amb ambient temperature in free air - 40 - +85 c
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 9 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 10. static characteristics table 7: static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit v cc = 2.5 v 0.2 v [1] v ik input diode voltage v cc = 2.3 v; i ik = - 18 ma - - 0.85 - 1.2 v v oh high-level output voltage v cc = 2.3 v to 3.6 v; i oh = - 100 m av cc - 0.2 -v v cc = 2.3 v; i oh = - 8 ma 1.8 - v v ol low-level output voltage v cc = 2.3 v; i ol = 100 m a - 0.07 0.2 v v cc = 2.3 v; i ol = 24 ma - 0.3 0.5 v v cc = 2.3 v; i ol = 8 ma - - 0.4 v v rst power-up low-state output voltage v cc = 2.7 v; i o = 1 ma; v i =v cc or gnd [2] - - 0.55 v i li input leakage current control pins v cc = 2.7 v; v i = v cc or gnd - 0.1 1 m a v cc = 0 v or 2.7 v; v i = 5.5 v 0.1 10 m a i/o data pins v cc = 0 v or 2.7 v; v i = 5.5 v [3] - 0.1 20 m a v cc = 2.7 v; v i = v cc [3] - 0.1 10 m a v cc = 2.7 v; v i = 0 v [3] - +0.1 - 5 m a i off power-down leakage current v cc = 0 v; v i or v o = 0 v to 4.5 v - 0.1 100 m a i hold bus hold current data inputs v cc = 2.3 v; v i = 0.7 v [4] -90- m a v cc = 2.3 v; v i = 1.7 v [4] - - 75 - m a i ex external current into output output in high-state when v o >v cc ; v o = 5.5 v; v cc = 2.3 v - 10 125 m a i pu , i pd power-up/down 3-state output current v cc 1.2 v; v o = 0.5 v to v cc ; v i = gnd or v cc ; oeab or oeab dont care [5] - 1 100 m a i cc supply current v cc = 2.7 v; v i = gnd or v cc ;i o =0a outputs high-state - 0.04 0.1 ma outputs low-state - 2.5 4.5 ma outputs disabled [6] - 0.04 0.1 ma d i cc additional supply current per input pin v cc = 2.3 v to 2.7 v; one input at v cc - 0.6 v, other inputs at v cc or gnd [7] - 0.01 0.4 ma c i input capacitance of control pins v i = 0 v or v cc 4- pf c io input/output capacitance of i/o pins v i/o = 0 v or v cc ; outputs disabled 8 - pf v cc = 3.3 v 0.3 v [8] v ik input diode voltage v cc = 3.0 v; i ik = - 18 ma - - 0.85 - 1.2 v v oh high-level output voltage v cc = 3.0 v to 3.6 v; i oh = - 100 m av cc - 0.2 v cc -v v cc = 3.0 v; i oh = - 32 ma 2.0 2.3 - v
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 10 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state [1] all typical values are at v cc = 2.5 v and t amb = 25 c. [2] for valid test results, data must not be loaded into the ?ip-?ops (or latches) after applying power. [3] unused pins at v cc or gnd. [4] not guaranteed. [5] this parameter is valid for any v cc between 0 v and 1.2 v with a transition time of up to 10 ms. from v cc =1.2vtov cc = 2.5 v 0.2 v a transition time of 100 m s is permitted. this parameter is valid for t amb =25 c only. [6] i cc is measured with outputs pulled up to v cc or pulled down to ground. [7] this is the increase in supply current for each input at the speci?ed voltage level other than v cc or gnd. [8] all typical values are at v cc = 3.3 v and t amb = 25 c. [9] this is the bus hold overdrive current required to force the input to the opposite logic state. [10] this parameter is valid for any v cc between 0 v and 1.2 v with a transition time of up to 10 ms. from v cc =1.2vtov cc = 3.3 v 0.3 v a transition time of 100 m s is permitted. this parameter is valid for t amb =25 c only. v ol low-level output voltage v cc = 3.0 v; i ol = 100 m a - 0.07 0.2 v v cc = 3.0 v; i ol = 16 ma - 0.25 0.4 v v cc = 3.0 v; i ol = 32 ma - 0.3 0.5 v v cc = 3.0 v; i ol = 64 ma - 0.4 0.55 v v rst power-up low-state output voltage v cc = 2.7 v; i o = 1 ma; v i =v cc or gnd [2] - - 0.55 v i li input leakage current control pins v cc = 3.6 v; v i = v cc or gnd - 0.1 1 m a v cc = 0 v or 3.6 v; v i = 5.5 v - 0.1 10 m a i/o data pins v cc = 3.6 v; v i = 5.5 v [3] - 0.1 20 m a v cc = 3.6 v; v i = v cc [3] - 0.5 10 m a v cc = 3.6 v; v i = 0 v [3] - +0.1 - 5 m a i off power-down leakage current v cc = 0 v; v i or v o = 0 v to 4.5 v - 0.1 100 m a i hold bus hold current data inputs v cc = 3 v; v i = 0.8 v [9] 75 130 - m a v cc = 3 v; v i = 2.0 v [9] - 75 - 140 - m a v cc = 0 v to 3.6 v; v cc = 3.6 v [9] 500 - - m a i ex external current into output output in high-state when v o >v cc ; v o = 5.5 v; v cc = 2.3 v - 10 125 m a i pu , i pd power-up/down 3-state output current v cc 1.2 v; v o = 0.5 v to v cc ; v i = gnd or v cc ; oeab or oeab dont care [10] -1 100 m a i cc supply current v cc = 3.6 v; v i = gnd or v cc ;i o =0a outputs high-state - 0.06 0.1 ma outputs low-state - 3.5 5 ma outputs disabled [6] - 0.06 0.1 ma d i cc additional supply current per input pin v cc = 3 v to 3.6 v; one input at v cc - 0.6 v, other inputs at v cc or gnd [7] - 0.04 0.4 ma c i input capacitance of control pins v i = 0 v or v cc 4- pf c io input/output capacitance of i/o pins v i/o = 0 v or v cc ; outputs disabled 8 - pf table 7: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 11 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 11. dynamic characteristics table 8: dynamic characteristics voltages are referenced to gnd (ground = 0 v); for test circuit see figure 11 . t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit v cc = 2.5 v 0.2 v [1] ; c l = 30 pf t phl propagation delay an to bn or bn to an see figure 5 1.4 2.2 3.5 ns leab to bn or leba to an see figure 6 1.5 2.5 4.0 ns cpab to bn or cpba to an see figure 7 1.9 3.2 5.2 ns t plh propagation delay an to bn or bn to an see figure 5 1.0 1.8 3.0 ns leab to bn or leba to an see figure 6 1.5 2.5 4.0 ns cpab to bn or cpba to an see figure 7 2.2 3.5 5.0 ns t phz output disable time from high-level see figure 9 2.2 3.1 4.4 ns t plz output disable time from low-level see figure 10 1.6 2.3 3.4 ns t pzh output enable time to high-level see figure 9 2.3 3.6 4.8 ns t pzl output enable time to low-level see figure 10 1.9 2.9 4.4 ns t h(h) hold time high an to cpab or bn to cpba see figure 8 0.0 - 1.1 - ns an to leab or bn to leab see figure 8 1.5 0.4 - ns ceab to cpab or ceba to cpba see figure 8 2.0 0.4 - ns t h(l) hold time low an to cpab or bn to cpba see figure 8 0.0 - 0.3 - ns an to leab or bn to leab see figure 8 1.9 1.0 - ns ceab to cpab or ceba to cpba see figure 8 +0.8 - 0.1 - ns t su(h) set-up time high an to cpab or bn to cpba see figure 8 2.0 0.4 - ns an to leab or bn to leba see figure 8 0.0 - 1.0 - ns ceab to cpab or ceba to cpba see figure 8 0.7 0.3 - ns t su(l) set-up time low an to cpab or bn to cpba see figure 8 2.0 1.2 - ns an to leab or bn to leba see figure 8 1.5 0.4 - ns ceab to cpab or ceba to cpba see figure 8 +0.3 - 0.4 - ns t wh pulse width high cpab or cpba see figure 7 3.0 - - ns leab or leba see figure 6 1.5 - - ns t wl pulse width low cpab or cpba see figure 7 3.0 - - ns
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 12 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state [1] all typical values are measured at v cc = 2.5 v and t amb = 25 c. [2] all typical values are measured at v cc = 3.3 v and t amb = 25 c. v cc = 3.3 v 0.3 v [2] ; c l = 50 pf t phl propagation delay an to bn or bn to an see figure 5 1.1 2.0 2.8 ns leab to bn or leba to an see figure 6 1.4 2.3 3.6 ns cpab to bn or cpba to an see figure 7 1.7 2.7 4.1 ns t plh propagation delay an to bn or bn to an see figure 5 1.2 1.9 2.9 ns leab to bn or leba to an see figure 6 1.5 2.5 3.8 ns cpab to bn or cpba to an see figure 7 2.1 3.1 4.5 ns t phz output disable time from high-level see figure 9 2.7 3.6 4.9 ns t plz output disable time from low-level see figure 10 2.1 2.8 4 ns t pzh output enable time to high-level see figure 9 2.2 3.2 4.2 ns t pzl output enable time to low-level see figure 10 1.6 2.5 3.8 ns t h(h) hold time high an to cpab or bn to cpba see figure 8 +1.0 - 0.5 - ns an to leab or bn to leab see figure 8 1.5 0.1 - ns ceab to cpab or ceba to cpba see figure 8 1.5 0.7 - ns t h(l) hold time low an to cpab or bn to cpba see figure 8 +1.0 - 0.3 - ns an to leab or bn to leab see figure 8 1.5 0.5 - ns ceab to cpab or ceba to cpba see figure 8 +1.0 - 0.3 - ns t su(h) set-up time high an to cpab or bn to cpba see figure 8 1.5 0.4 - ns an to leab or bn to leba see figure 8 +1.0 - 0.5 - ns ceab to cpab or ceba to cpba see figure 8 1.5 0.3 - ns t su(l) set-up time low an to cpab or bn to cpba see figure 8 1.5 0.6 - ns an to leab or bn to leba see figure 8 +1.0 - 0.1 - ns ceab to cpab or ceba to cpba see figure 8 1.0 - 0.4 - ns t wh pulse width high cpab or cpba see figure 7 2.0 - - ns leab or leba see figure 6 1.5 - - ns t wl pulse width low cpab or cpba see figure 7 2.0 - - ns table 8: dynamic characteristics continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 11 . t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 13 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 12. waveforms measurement points are given in t ab le 9 . v ol and v oh are typical voltage output drop that occur with the output load. fig 5. propagation delay input (an, bn) to output (bn, an) in transparent mode measurement points are given in t ab le 9 . v ol and v oh are typical voltage output drop that occur with the output load. fig 6. propagation delay latch enable (leab, leba) to output (an, bn) and latch enable (leab, leba) pulse width measurement points are given in t ab le 9 . v ol and v oh are typical voltage output drop that occur with the output load. fig 7. propagation delay clock input (cpab, cpba) to output (an, bn), clock pulse width (cpab, cpba) and maximum clock frequency (cpab, cpba) 001aad308 output bn or an input an or bn v m v m t phl t plh v m v m v oh v i 0 v v ol 001aad310 v m v m v m v m v m t plh t phl t wh input leab or leba output an or bn v oh v ol v i 0 v 001aad254 v m v m v m v m v m t plh t phl t wl t wh input cpba or cpab output an or bn 1/f max v oh v i v ol 0 v
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 14 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state measurement points are given in t ab le 9 . the shaded areas indicate when the input is permitted to change for predictable output performance. fig 8. data set-up and hold times measurement points are given in t ab le 9 . v oh is typical voltage output drop that occur with the output load. fig 9. 3-state output enable time to high-level and output disable time from high-level measurement points are given in t ab le 9 . v ol is typical voltage output drop that occur with the output load. fig 10. 3-state output enable time to low-level and output disable time from low-level 001aad255 v m v m v m v m v i v i v m v m t su(h) t h(h) t su(l) t h(l) 0 v 0 v input an, bn, ceab, ceba input leab or leba, cpab or cpba 001aad309 input oeba or oeab output an or bn v m v y v m t phz t pzh v m v oh v i 0 v 0 v 001aad311 input oeba or oeab output an or bn v m v m v x t plz t pzl v m 0 v v ol v i 3.0 v or v cc
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 15 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state table 9: measurement points supply voltage input output v m v m v x v y 3 3 v 1.5 v 1.5 v v ol + 0.3 v v oh - 0.3 v 2.7 v 0.5 v cc 0.5 v cc v ol + 0.15 v v oh - 0.15 v measurement points are given in t ab le 9 . a. input pulse de?nition test data is given in t ab le 10 . de?nitions test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = test voltage for switching times. b. test circuit fig 11. load circuitry for switching times table 10: test data input load v ext v i f i t w t r , t f c l r l t plz , t pzl t plh , t phl t phz ,t pzh 3.0 v or v cc whichever is less 10 mhz 500 ns 2.5 ns 30 pf or 50 pf 500 w 6 v or 2 v cc open gnd 001aac221 v m v m t w t w 10 % 90 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % 10 % t thl (t f ) t tlh (t r ) t tlh (t r ) t thl (t f ) v ext v cc v i v o mna616 dut c l r t r l r l pulse generator
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 16 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 13. package outline fig 12. package outline sot371-1 (ssop56) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.0 0.6 1.2 1.0 0.85 0.40 8 0 o o 0.18 0.25 1.4 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot371-1 99-12-27 03-02-18 (1) w m b p d h e e z e c v m a x a y 56 29 mo-118 28 1 q a a 1 a 2 l p q detail x l (a ) 3 pin 1 index 0 5 10 mm scale ssop56: plastic shrink small outline package; 56 leads; body width 7.5 mm sot371-1 a max. 2.8
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 17 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state fig 13. package outline sot364-1 (tssop56) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot364-1 99-12-27 03-02-19 w m q a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 128 56 29 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 1 8.3 7.9 0.50 0.35 0.5 0.1 0.08 0.25 0.8 0.4 p e v m a a tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364-1 a max. 1.2 0 2.5 5 mm scale mo-153
74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 18 of 20 philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 14. revision history table 11: revision history document id release date data sheet status change notice doc. number supersedes 74ALVT16601_3 20050705 product data sheet - - 74ALVT16601_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new presentation and information standard of philips semiconductors. ? section 2 f eatures : modi?ed jedec std 17 into jesd78. ? t ab le 8 dynamic char acter istics : changed values of propagation delay, output enable and output disable time. 74ALVT16601_2 19980213 product speci?cation - 9397 750 03571 74ALVT16601_1 74ALVT16601_1 - - - - -
philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 74ALVT16601_3 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 03 5 july 2005 19 of 20 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. 19. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 5 july 2005 document number: 74ALVT16601_3 published in the netherlands philips semiconductors 74ALVT16601 18-bit universal bus transceiver; 3-state 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 7 7.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 recommended operating conditions. . . . . . . . 8 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 9 11 dynamic characteristics . . . . . . . . . . . . . . . . . 11 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 contact information . . . . . . . . . . . . . . . . . . . . 19

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